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cy7c1020cv26 512 kb (32 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05406 rev. *d revised august 16, 2011 features temperature range ? automotive: ?40 c to 125 c high speed ? t aa = 15 ns optimized voltage range: 2.5 v to 2.7 v automatic power down when deselected independent control of upper and lower bits cmos for optimum speed and power package offered: 44-pin tsop ii functional description the cy7c1020cv26 is a high performance cmos static ram organized as 32,768 words by 16 bits. this device has an automatic power down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 1 through i/o 8 ), is written into the location specified on the address pins (a 0 through a 14 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 9 through i/o 16 ) is written into the location specified on the address pins (a 0 through a 14 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on i/o 1 to i/o 8 . if byte high enable (bhe ) is low, then data from memory appears on i/o 9 to i/o 16 . see the truth table on page 7 for a complete description of read and write modes. the input/output pins (i/o 1 through i/o 16 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1020cv26 is available in a standard 44-pin tsop type ii. logic block diagram
cy7c1020cv26 document #: 38-05406 rev. *d page 2 of 11 pin configuration figure 1. 44-pin tsop ii (top view) selection guide description cy7c1020cv26-15 unit maximum access time 15 ns maximum operating current 100 ma maximum cmos standby current 5 ma
cy7c1020cv26 document #: 38-05406 rev. *d page 3 of 11 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ..... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [1] .....?0.5 v to +4.6 v dc voltage applied to outputs in high-z state [1] .................................... ?0.5 v to v cc +0.5 v dc input voltage [1] ................................. ?0.5 v to v cc +0.5 v current into outputs (low) ......................................... 20 ma static discharge voltage........................................... > 2001 v (per mil-std-883, method 3015) latch up current...................................................... > 200 ma operating range range ambient temperature v cc automotive ?40 ? c to +125 ? c 2.5 v to 2.7 v electrical characteristics over the operating range parameter description test conditions cy7c1020cv26 unit min max v oh output high voltage v cc = minimum, i oh = ?1.0 ma 2.3 v v ol output low voltage v cc = minimum, i ol = 1.0 ma 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [1] ?0.3 0.8 v i ix input load current gnd < v i < v cc ?5 +5 ? a i oz output leakage current gnd < v i < v cc , output disabled ?5 +5 ? a i os [2] output short circuit current v cc = maximum, v out = gnd ?300 ma i cc v cc operating supply current v cc = maximum, i out = 0 ma, f=f max = 1/t rc 100 ma i sb1 automatic ce power-down current ?ttl inputs maximum v cc , ce > v ih v in > v ih or v in < v il , f = f max 40 ma i sb2 automatic ce power-down current ?cmos inputs maximum v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 5 ma capacitance [3] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 2.6 v 8 pf c out output capacitance 8 pf notes 1. vil (min.) = ?2.0v for pulse durations of less than 20 ns. 2. not more than one output should be shorted at one time. duration of the short circui t should not exceed 30 seconds. 3. tested initially and after any design or proces s changes that may affect these parameters.
cy7c1020cv26 document #: 38-05406 rev. *d page 4 of 11 figure 2. ac test loads and waveforms [4] ac switching ch aracteristics over the operating range parameter description cy7c1020cv26 unit min max read cycle t rc read cycle time 15 ns t aa address to data valid 15 ns t oha data hold from address change 3 ns t ace ce low to data valid 15 ns t doe oe low to data valid 7 ns t lzoe oe low to low z [5] 0 ns t hzoe oe high to high z [5, 6] 7 ns t lzce ce low to low z [5] 3 ns t hzce ce high to high z [5, 6] 7 ns t pu [7] ce low to power-up 0 ns t pd [7] ce high to power-down 15 ns t dbe byte enable to data valid 7 ns t lzbe byte enable to low z 0 ns t hzbe byte disable to high z 7 ns write cycle [8] t wc write cycle time 15 ns t sce ce low to write end 10 ns t aw address setup to write end 10 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 10 ns t sd data setup to write end 8 ns t hd data hold from write end 0 ns t lzwe we high to low z [5] 3 ns t hzwe we low to high z [5, 6] 4 ns t bw byte enable to end of write 10 ns 90% 10% 2.5v gnd 90% 10% all input pulses rise time: 1 v/ns fall time:1 v/ns 2.6v output 30 pf r 1830 ? r2 1976 ? (a) (b) notes 4. test conditions assume signal transition time of 1v/ns or less , timing reference levels of 1.3 v, input pulse levels of 0 to 2.5 v and transmission line loads as in (a) of ac test loads. 5. at any temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 6. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured 500 mv from steady-state vol tage. 7. this parameter is guaranteed by design and is not) 8. the internal write time of the memory is defined by the overlap of ce low, we low and bhe / ble low. ce, we and bhe / ble mus t be low to initiate a write, and the transition of these signals can terminate the write. th e input data setup and hold timing should be referenced to the l eading edge of the signal that terminates
cy7c1020cv26 document #: 38-05406 rev. *d page 5 of 11 switching waveforms figure 3. read cycle no. 1 [9, 10] figure 4. read cycle no. 2 (oe controlled) [10, 11] notes 9. device is continuously selected. oe , ce , bhe and/or bhe = v il . 10. we is high for read cycle. 11. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb
cy7c1020cv26 document #: 38-05406 rev. *d page 6 of 11 figure 5. write cycle no. 1 (ce controlled) [12, 13] figure 6. write cycle no. 2 (ble or bhe controlled) notes 12. data i/o is high impedance if oe or bhe and ble = v ih . 13. if ce goes high simultaneously with we going high, the output remains in a high impedance state. switching waveforms t hd t sd t sce t sa t ha t aw t pwe t wc bw data i/o address ce we bhe, ble t t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce
cy7c1020cv26 document #: 38-05406 rev. *d page 7 of 11 figure 7. write cycle no. 3 (we controlled, oe low) truth table ce oe we ble bhe i/o 1 ?i/o 8 i/o 9 ?i/o 16 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high z read ? lower bits only active (i cc ) h l high z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high z write ? lower bits only active (i cc ) h l high z data in write ? upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc ) switching waveforms t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe
cy7c1020cv26 document #: 38-05406 rev. *d page 8 of 11 ordering information speed (ns) ordering code package name package type operating range 15 CY7C1020CV26-15ZSXE z44 44-pin tsop type ii (pb-free) automotive ordering code definitions temperature range: e = automotive package type: zsx = 44-pin tsop type ii (pb-free) speed grade= 15 ns v26 = voltage range (2.5 v to 2.7 v) c = 0.16 m technology 0 = data width 16-bits 02 = 512-kbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - 15 zsx 7 02 v26 e c 0
cy7c1020cv26 document #: 38-05406 rev. *d page 9 of 11 package diagrams figure 8. 44-pin tsop ii 51-85087 *c
cy7c1020cv26 document #: 38-05406 rev. *d page 10 of 11 document history page document title: cy7c1020cv26 512 kb (32 k 16) static ram document number: 38-05406 rev. ecn no. submission date orig. of change description of change ** 128060 07/30/03 ejh customized data sheet to meet special requirements for cg5988af automotive temperature range: ?40c / +125c *a 352999 see ecn syt removed ?cg5988af? from the datasheet edited the features section for better structure on page 1 edited the title to include the mention of ?512kb? *b 2903127 04/01/2010 vivg updated template. updated package diagram. added sales, solutions, and legal information . *c 3109992 12/14/2010 aju added ordering code definitions . *d 3346414 08/16/2011 rame update ordering code definitions
document #: 38-05406 rev. *d revised august 16, 2011 page 11 of 11 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1020cv26 ? cypress semiconductor corporation, 2003-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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